This invention relates to an apparatus and method for deriving test signals for an integrated circuit ("IC") under test. More particularly, this invention relates to a method and apparatus for deriving test signals by signal compression of prior test responses.
To test an IC, test signals are applied to select test points, while responses are sensed. As ICs become more complex, more test points are needed to test internal circuit elements. As a result, complex ICs often are designed with internal test circuitry which accommodates extensive testing. Such internal test circuitry may include shift registers which receive test signal patterns to be shifted out of the register to various test points. Accordingly, one or more external pins are used for entering test signals to such shift registers for being relayed to multiple internal test points.
Such an approach is commonly referred to as SCAN. See "Design For testability --A Survey" by T.W. Williams and K.P. Parker, Proceedings IEEE, Vol 71, pp. 98-112, January 1983; and "A Logic Design Structure For LSI Testing" by E.B. Eichelberger and T.W. Williams, Proceedings 14th Design Automation Conference, June 1977 77CH1216-1C, pp. 462-468. Also see "Built-in Self-Test Techniques" and "Built-in Self-Test Structures" by E.J. McCluskey, IEEE Design and Test, Vol. 2, No. 2, pp. 437-452. Also see U.S. Pat. Nos. 3,806,891 (Eichelberger et. al.); 4,293,919 (Dasgupta et. al.) and 4,513,418 (Bardell, Jr. et. al.) assigned to the IBM Corporation which disclose the serial connection of flip-flops into a shift register to allow access to them through "fewer" test points.
According to the SCAN approach, the integrated circuit is designed to tie select storage elements (e.g., test points) to one or more shift register chains. The shift registers are loaded through test contacts or through the primary input pins during a test, enabling the desired logic states to be loaded to the select storage elements Thus, the test signals are generated off-chip and multiplexed to the appropriate test point.
According to built-in self test ("BIST) approaches a test pattern is stored in an on-chip ROM device or is generated as a pseudo-random pattern using an on-chip device. Such BIST approaches typically are used for on-line or off-line testing in which signals are not applied at the primary input pins once the test commences.
Other approaches for defining test signals and monitoring internal IC components are described in U.S. Pat. No. 4,613,970 for INTEGRATED CIRCUIT DEVICE AND METHOD OF DIAGNOSING THE SAME; EPO patent publication number 223 714 A2 for SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH TEST CIRCUIT; U.S. Pat. No. 4,517,672 for METHOD AND ARRANGEMENT FOR AN OPERATIONAL CHECK OF A PROGRAMMABLE LOGIC ARRAY; IBM Technical Disclosure Bulletin Vol. 8, no. 5 Oct. 1965, "Voltage Checking Device" by G. Canard and A. Potocki; and U.S. Pat. No. 3,795,859 for METHOD AND APPARATUS FOR DETERMINING THE ELECTRICAL CHARACTERISTICS OF A MEMORY CELL HAVING FIELD EFFECT TRANSISTORS.